The present invention relates to a novel circuit board, whereon semiconductors and the like are mounted, and a method of manufacturing the same; and more particularly, the invention relates to a circuit board having via-holes filled with metal for connecting interlayer conductor wiring, and a method of manufacturing the same.
The technology to fill holes, which are formed in an insulator, with metal is applied to the technology for interlayer connection of high density circuit boards, such as a LSI, a thin film multilayered board, a build up board, and the like. For the interlayer connection of an LSI, wet metallizing methods, such as plating and the like, are not used, but dry metallizing such as spattering, CVD (chemical vapor deposition method), and the like are used. For instance, a method of filling aluminum into via-holes by the spattering method is disclosed in JP-A-6-168907 (1994). A method of filling tungsten into contact holes by a monosilan reduction CVD method of tungsten fluoride, or hydrogen reduction CVD method is disclosed in JP-A-8-31932 (1996). Furthermore, a method of forming a connecting plug of copper by a CVD method using an organo copper compound as a raw material is disclosed in JP-A-6-236879 (1994).
However, since all these methods are dry metallization methods and methods for processing which use an apparatus provided with a vacuum system, these methods have problems, such as a high equipment cost and a low through-put. Furthermore, so-called PVD methods (physical vapor deposition method), such as a spattering method and the like, do not have selectivity in forming a film, and so a metallic film must be formed on the whole surface of the substrate uniformly. Therefore, it is impossible to metallize only the interlayer connecting portion. On the other hand, a film formed by the CVD method has problems, such as a large content of impurities and a low purity. The decrease in purity causes such problems as an increase in the electrical resistance and a decrease in the reliability.
Regarding thin film multilayered substrates and build-up substrates, a method of filling micro via-holes using the techniques of electroless plating or electroplating has been disclosed, but control of film thickness is difficult. For instance, In accordance with JP-A-6-302965 (1994), the via-holes are filled by plating. However, in this case, since the control of the plated film thickness is extremely difficult, a final polishing step is required. A method of filling the inside of via-holes by electroplating or electroless plating has been disclosed in JP-A-5-335713 (1993). However, in accordance with the above prior arts the filling of the via-holes by electroless plating is impossible. Because the electroless plating reaction proceeds also on the end plane of the conductor surface at the upper layer of the via-holes, the opening of the via-hole is decreased with elapsed plating time and finally is closed. In this case, a space in the form of a void remains inside the via-hole, and the reliability of the substrate is significantly decreased.
In the case of electroplating, the plating reaction proceeds at the end plane of the conductor surface at the upper layer of the via-holes from the moment when the metal plated from the bottom portion of the via-hole reaches the end plane of the conductor surface at the upper layer of the via-holes, and so the opening of the via-hole will become closed in those cases where the diameter of the via-hole is less than two times the conductor thickness. In this case, a space in the form of a void again remains inside the via-hole, resulting in a problem in that the reliability of the substrate is significantly decreased. When the diameter of the via-hole is larger than two times the conductor thickness, the opening of the via-hole will not become closed, but the shape of the plating, when it reaches the conductor surface, is not xe2x80x9ccolumnarxe2x80x9d like the shape when plating the inside of the via-hole, but is xe2x80x9ca mushroom shapexe2x80x9d. This is because the plating reaction does not indicate any anisotropy, but the metal grows in an isotropic manner.
As explained above, when filling metal into a micro hole using a dry metallizing method, problems occur in that the manufacturing steps become complex because the PVD method does not have selectivity, and so a polishing step becomes necessary, and in that the production yield is decreased because the stress applied to the substrate when polishing is significant. Because the CVD method uses a compound containing a chemical element other than a metal as the raw material, the obtained metal contains a large amount of impurities. The increase in impurity concentration causes problems, such as an increase in the electric resistance, a decrease in the reliability, and the like. The problems inherent in use of the metallizing method as a whole are a high apparatus cost, because the apparatus requires a vacuum system, and a low through-put.
On the contrary, when filling metal into a micro hole using a wet metallizing method, either the electroplating method or the electroless plating method can be used.
In accordance with the electroplating method, an electricity supplying layer for supplying an electric current for the plating is required as a base layer. A first conductive layer is previously not used for patterning, but necessarily is used as the electricity supplying layer first. Accordingly, the inside of the via-holes is filled by plating first, then, the insulating layer is peeled off, and patterning of the first conductive layer is performed. Subsequently, the insulating layer is formed again, and polishing is performed in order to flatten the surface and determine the via-hole filling metal. The polishing step is one of the problems, because the step requires a long time, and this decreases the production yield because the stress applied to the substrate is significant.
When the electroless plating method is used, the plating reaction proceeds from only the surface of a first conductive layer, and the inside of the via-hole is filled with the plated metal. In this case, a second conductive layer on the surface of the insulating layer is necessarily formed after filling the via-holes. Because, if the plating is performed in the presence of the second conductive layer, the plating reaction also will proceed from the surface of the second conductive layer, and the openings of the via-holes will close. When the plating reaction proceeds from the surface of the first conductive layer to fill the inside of the via-holes with the plated metal, control of the plated film thickness is extremely difficult. When the plated film thickness is small, a break in the wiring is possible, and when the plated film thickness is large, the flatness of the surface is lost, and so problems are generated informing the multilayered structure.
Therefore, in accordance with the prior art, the inside of the via-holes has been filled with metal by the steps of thickening the plated film thickness somewhat, causing the plated metal to protrude from the insulating layer, in order to eliminate possibility of a break in the wiring caused by deficiency of the plated film thickness, and subsequently, polishing off the excess portion of the plated metal to flatten the surface. However, the polishing step in this process requires a long time, as explained above, and the production yield is decreased by the significantly large stress applied to the substrate.
One of the objects of the present invention is to provide a circuit board, which makes it possible to identify via-hole portions, on the surface of a substrate, in order to facilitate formation of a multilayered structure with the substrate, which via-holes have been previously filled with metal.
The second object of the present invention is to provide a method of manufacturing a circuit board, which makes it possible to fill metal into the via-holes with good reproducibility and uniformly, by electroless plating, a process with which it has been difficult heretofore to control the film thickness.
In accordance with the present invention, when via-holes are filled by electroless plating, the plating is performed while applying a potential higher than the reaction potential of the electroless plating reaction to the surface conducting layer. The electroless plating grows upwards from the bottom of the via-hole, and the via-hole is completely filled. When the plated metal filling the via-hole reaches the surface conducting layer, the electroless plating reaction automatically stops, because the surface conducting layer is charged with a potential higher than the reaction potential of the electroless plating reaction by the external power supply. As explained above, the plating reaction can be stopped entirely when the plated metal surface reaches the surface conducting layer in all the via-holes. Therefore, it becomes possible to control, with good reproducibility and uniformly, the thickness of the plated metal, which heretofore has been extremely difficult to control.
In accordance with the circuit board manufactured by the method of the present invention, the via-hole portion can be identified, even after a conducting layer covering surfaces of both the via-holes filled with the plated metal and the insulating layer are formed, by observing the surface of the conducting layer.
The circuit board of the present invention includes a conductor connecting portion having a structure such that a first conductor is formed on an insulating substrate, an insulating layer is formed on the insulating substrate and the first conductor, a second conductor is formed on the insulating layer, via-hole for electrically connecting the first conductor and the second conductor are formed in the insulating layer, and the inside of the via-holes are filled with a third conductor, the invention being characterized in that the via-hole portion can be identified from a surface condition of a fourth conductor covering the surface of both the second conductor and a third conductor. In this regard, the surface condition of the fourth conductor differs from the surface of the second conductor and the third conductor, or the surface condition of the fourth conductor changes on a boundary region of the second conductor and the third conductor.
The identification of the via-hole from the surface of the fourth conductor can be performed, for instance, by visual observation with a microscope, methods of utilizing differences in reflective index, or luster, or an optical method, such as image analysis and the like.
Further, the circuit board of the present invention includes a conductor connecting portion having a structure such that a first conductor is formed on an insulating substrate, an insulating layer is formed on the insulating substrate and the first conductor, a second conductor is formed on the insulating layer, via-holes for electrically connecting the first conductor and the second conductor are formed in the insulating layer, and the inside of the via-holes are filled with a third conductor, the invention being characterized in that, for a circuit board comprising a fourth conductor covering the surface of both the second conductor and a third conductor, the fourth conductor is formed to have an area in the shape of dent above the third conductor.
Furthermore, the circuit board of the present invention includes a conductor connecting portion having a structure such that a first conductor is formed on an insulating substrate, an insulating layer is formed on the insulating substrate and the first conductor, a second conductor is formed on the insulating layer, via-holes for electrically connecting the first conductor and the second conductor are formed in the insulating layer, and the inside of the via-holes are filled with a third conductor, the invention being characterized in that, the circuit board is provided with a fourth conductor covering the surface of both the second conductor and a third conductor.
Furthermore, the circuit board of the present invention includes a conductor connecting portion having a structure such that a first conductor is formed on an insulating substrate, an insulating layer is formed on the insulating substrate and the first conductor, a second conductor is formed on the insulating layer, via-hole for electrically connecting the first conductor and the second conductor are formed in the insulating layer, the inside of the via-holes are filled with a third conductor, and a fourth conductor covers the surface of both the second conductor and the third conductor, the invention being characterized in that the third conductor has the same height as the thickness of the insulating layer.
A method of the present invention for manufacturing a circuit board, which includes a first conductor formed on an insulating substrate, an insulating layer formed on the insulating substrate and the first conductor, a second conductor formed on the insulating layer, via-holes for electrically connecting the first conductor and the second conductor formed in the insulating layer, and metal filling the inside of the via-holes, is characterized by filling the inside of the via-holes with plated metal by applying a potential higher than the potential of the plating reaction to the second conductor when the third conductor is filled into the via-holes by electroless plating, and the electroless plating reaction is initiated from the first conductor at the bottom of the via-hole.
Further, a method of the present invention for manufacturing a circuit board is characterized by the steps of forming an insulating layer onto an insulating substrate having a first conductor on its surface, forming a second conductor on the insulating layer, patterning the second conductor, forming via-holes into the insulating layer on the first conductor using the second conductor as a mask, and forming a third conductor by filling metal into the via-holes by electroless plating onto the first conductor at the bottom of the via-hole while applying a potential higher than the potential of the plating reaction to the second conductor.
Furthermore, a method of the present invention for manufacturing a circuit board is characterized by the steps of laminating an insulating layer in a film shape having a second conductor on its surface onto an insulating substrate having a first conductor on the surface thereof, patterning the second conductor, forming via-holes into the insulating layer reaching the first conductor using the second conductor as a mask, and forming a third conductor by filling metal into the via-holes by electroless plating onto the first conductor at the bottom of each via-hole while applying a potential higher than the potential of the plating reaction to the second conductor.
In accordance with the present invention, the object of the invention is achieved by forming a second conductor at a location where it is insulated electrically and is separated from a substrate which is going to be plated by a distance to be plated, as explained above, and performing electroless plating while applying a potential higher than the potential of the plating reaction to the second conductor.
The method of electroless plating of the present invention includes the steps of forming a first conductor, and a second conductor which is insulated electrically from the first conductor, on a substrate which is going to be plated, and mounting a further conductor on the surface of the first conductor by electroless plating, characterized in that a potential higher than the potential of the plating reaction is applied to the second conductor.
When filling a desired amount of metal into micro holes or grooves by electroless plating, a potential higher than the potential of the plating reaction is applied to a second conductor on the surface of the insulating layer in the vicinity of the micro holes or the grooves from an external power source.
The method of electroless plating of the present invention includes the steps of forming holes or grooves in a substrate which is going to be plated, forming a second conductor in the vicinity of the holes or the grooves on an insulating body, and effecting an electroless plating reaction originated from the first conductor so as to fill metal into the holes or the grooves, characterized in that a potential higher than the potential of the plating reaction is applied to the second conductor from an exterior power source.
The potential to be applied to the second conductor is desirably +0.1-+1.5 Volt relative to the potential of the electroless reaction, and preferably is +0.4-+0.7 Volt.
Typical examples of the micro holes to be filled with metal according to the present invention are interlayer connecting portions of an IC, interlayer connecting portions of thin film multilayered circuit boards or printed circuit boards, and the like. However, the present invention can be applied additionally to the filling of metal into arbitrary blind holes formed in an insulator. The shape and material of the insulating body having the holes to be filled with metal are not specified particularly. The structures to which the present invention can be applied are not only holes but also grooves, and the present invention is applicable to the step of forming circuits.
In a module including a multilayered thin film circuit board, which is manufactured by laminating plural insulating layers having micro circuit patterns formed on their surface, and mounting semiconductor elements on at least one side plane of the circuit board, the present invention is characterized in that the multilayered thin film circuit board is composed of the circuit board described previously.
In a mounted device of a large scale computer comprising module substrates mounted and connected to printed boards via connecting pins; multilayered thin film circuit boards, which are manufactured by laminating plural insulating layers having micro circuit patterns formed on their surface, and mounting semiconductor elements on at least one side plane of the circuit board, the present invention is characterized in that the multilayered thin film circuit board is composed of the circuit board described previously.